发明名称 FAULT TOLERANT COMPUTER AND TRANSACTION SYNCHRONOUS CONTROL METHOD THEREFOR
摘要 PROBLEM TO BE SOLVED: To provide a fault tolerant computer and a transaction synchronous control method, for automatically recovering synchronization between processors, in the event of out-of-step of a transaction of synchronous CPUs, without causing degeneracy of a processor. SOLUTION: The fault tolerant computer 8 comprises redundant arithmetic processing units 11 and 12, redundant input and output units 21 and 22, and a detection part 160. The arithmetic processing units 11 and 12 perform lock step operation, and out-of-step thereof is detected by the detection part 160. The input and output unit 21 and 22 include a transaction comparative control part for controlling, upon detection of out-of-step by the detection part 160, flows of transactions output from the arithmetic processing units 11 and 12. COPYRIGHT: (C)2008,JPO&INPIT
申请公布号 JP2008046942(A) 申请公布日期 2008.02.28
申请号 JP20060222902 申请日期 2006.08.18
申请人 NEC CORP 发明人 MIZUTANI FUMITOSHI
分类号 G06F11/20 主分类号 G06F11/20
代理机构 代理人
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