发明名称 |
APPARATUS FOR IMPLEMENTING PROCESSOR BUS SPECULATIVE DATA COMPLETION |
摘要 |
A method, and apparatus are provided for implementing processor bus speculative data completion in a computer system. A memory controller in the computer system sends uncorrected data from a memory to a processor bus. The memory controller also applies the uncorrected data to error correcting code (ECC) checking and correcting circuit. When a single bit error (SBE) is detected, corrected data is sent to the processor bus a predefined number of cycles after the uncorrected data.
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申请公布号 |
US2008222489(A1) |
申请公布日期 |
2008.09.11 |
申请号 |
US20080127118 |
申请日期 |
2008.05.27 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
BARRETT WAYNE MELVIN;HILLIER PHILIP ROGERS;KIRSCHT JOSEPH ALLEN;MCGLONE ELIZABETH A. |
分类号 |
G06F11/10 |
主分类号 |
G06F11/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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