Multiple-Port SRAM Device

摘要

A multiple-port memory cell includes first conductive lines in a first metal layer, second conductive lines in a second metal layer, third conductive lines a third metal layer, and fourth conductive lines in a fourth metal layer. The first conductive lines include a write bit line electrically coupled with a write bit line node; a first read bit line electrically coupled with a first read bit line node; and a second read bit line electrically coupled with a second read bit line node. The second conductive lines include a write word line electrically coupled with a write word line node. The fourth conductive lines include a first read word line electrically coupled with a first read word line node; and a second read word line electrically coupled with a second read word line node.

主权项

1. A memory circuit, comprising:
a memory cell including at least six transistors forming a storage node, each transistor in the storage node being formed in at least one fin structure, respectively; the memory cell further including a first read port and a second read port, each read port including two at least two additional transistors the additional transistors also being formed in at least one fin structure, respectively; wherein each fin structure of the memory cell extends in a first direction; a plurality of first conductive lines extending along the first direction, the plurality of first conductive lines comprising:
a first supply voltage line electrically coupled with a supply voltage node of the memory cell;a first reference voltage line electrically coupled with a first reference voltage node of the memory cell;a first write bit line electrically coupled with a first write bit line node of the memory cell;a first read bit line electrically coupled with a first read bit line node of the memory cell; anda second read bit line electrically coupled with a second read bit line node of the memory cell; a plurality of second conductive lines extending along a second direction orthogonal to the first direction, the plurality of second conductive lines comprising:
a write word line electrically coupled with a first write word line node of the memory cell; a plurality of third conductive lines extending along the first direction; and a plurality of fourth conductive lines extending along the second direction, the plurality of fourth conductive lines comprising:
a first read word line electrically coupled with a first read word line node of the memory cell; anda second read word line electrically coupled with a second read word line node of the memory cell.