System and method for calibration of a memory interface

摘要

A system includes memory unit having one or more storage arrays, and a memory interface unit that may be coupled between a memory controller and the memory unit. The memory interface unit may include a timing unit that may generate timing signals for controlling read and write access to the memory unit, and a control unit that may calibrate the timing unit at predetermined intervals. However, in response to an occurrence of a given predetermined interval, the memory interface unit may be configured to calibrate the timing unit using a number of partial calibration segments.

主权项

1. A system comprising:
a memory unit including one or more storage arrays; a memory interface unit coupled between a memory controller and the memory unit,
wherein the memory interface unit includes:a timing unit configured to generate timing signals for controlling read and write access to the memory unit; anda control unit configured to calibrate the timing unit at predetermined intervals in response to a determination that a current delay code of a Delay-Locked Loop (DLL) is greater than a stored delay code by at least a predetermined threshold value using a plurality of partial calibration segments.