发明名称 |
Saving power when in or transitioning to a static mode of a processor |
摘要 |
A method for reducing power utilized by a processor including the steps of determining that a processor is transitioning from a computing mode to a mode is which system clock to the processor is disabled, and reducing core voltage to the processor to a value sufficient to maintain state during the mode in which system clock is disabled. |
申请公布号 |
US9436264(B2) |
申请公布日期 |
2016.09.06 |
申请号 |
US201112987423 |
申请日期 |
2011.01.10 |
申请人 |
Intellectual Ventures Holding 81 LLC |
发明人 |
Read Andrew;Halepete Sameer;Klayman Keith |
分类号 |
G06F1/32;G06F1/26 |
主分类号 |
G06F1/32 |
代理机构 |
|
代理人 |
|
主权项 |
1. A method comprising:
transitioning a processor to a reduced operation mode within a variable time allowed that varies based on a processor configuration; and reducing a voltage to the processor by a value dependent on the variable time allowed, wherein the voltage reduced by the value varies with a variation in the voltage and is sufficient to retain a memory state of the processor while the processor operates in the reduced operation mode. |
地址 |
Las Vegas NV US |