发明名称 ARITHMETIC PROCESSING UNIT, INFORMATION PROCESSOR, AND CONTROL METHOD FOR INFORMATION PROCESSOR
摘要 PROBLEM TO BE SOLVED: To perform, in an arithmetic processing unit for processing data input from a plurality of transmission sources, appropriate adjustment of a bus use rate of each transmission source while suppressing increase in circuit scale.SOLUTION: An arithmetic processing unit includes a plurality of selection circuits 3 connected in series. At least one selection circuit 3 includes: a selection unit 34b for selecting a first input unit 33 from two or more input units 33, each of which receives, as input, data and identification information on a transmission source of the data from the transmission source or a selection circuit 3 at a prior stage, on the basis of the two or more pieces of identification information and priority information showing priority of each of a selection circuit 3 on the upstream side of the own selection circuit 3 and a plurality of transmission sources connected to the own selection circuit 3; an updating unit 34b for updating priority on a first transmission source shown by first identification information input to the first input unit 33, of the priority information; and a transfer unit 35a for transferring data input from the first input unit 33 and the first identification information to a transfer destination.SELECTED DRAWING: Figure 10
申请公布号 JP2016167726(A) 申请公布日期 2016.09.15
申请号 JP20150046691 申请日期 2015.03.10
申请人 FUJITSU LTD 发明人 KITAMURA YASUHIRO
分类号 H04L12/771;G06F15/173;H04L12/28;H04L12/851 主分类号 H04L12/771
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