Method of applying vertex based corrections to a semiconductor design

摘要

The invention discloses an improved method of geometry corrections to be applied to properly transfer semiconductor designs on a wafer or a mask in nanometer scale processes. In contrast with some prior art techniques, geometry corrections and possibly dose corrections are applied before fracturing. Unlike edge based corrections, where the edges are displaced in parallel, the displacements applied to generated geometry corrections according to the invention do not preserve parallelism of the edges, which is specifically well suited for free form designs. A seed design is generated from the target design. Vertices connecting segments are placed along the seed design contour. Correction sites are placed on the segments. Displacement vectors are applied to the vertices. A simulated contour is generated and compared to the contour of the target design. The process is iterated until a match criteria between simulated and target design (or another stop criteria) is reached.