SELECTIVE POWER GATING TO EXTEND THE LIFETIME OF SLEEP FETS

摘要

A power-gating array configured to power gate a logic block includes multiple zones of sleep field-effect transistors (FETs). A zone controller coupled to the power-gating array selectively enables a certain number of zones within the array depending on the voltage drawn by the logic block. When the logic block draws a lower voltage, the zone controller enables a lower number of zones. When the logic block draws a higher voltage, the zone controller enables a greater number of zones. One advantage of the disclosed technique is that sleep FET usage is reduced, thereby countering the effects of FET deterioration due to BTI and TDDB. Accordingly, the lifetime of sleep FETs configured to perform power gating for logic blocks may be extended.

主权项

1. A computer-implemented method for power gating a logic block, the method comprising:
adjusting an operating voltage associated with the logic block to a first voltage level; enabling a first subset of switching elements included in a set of switching elements that is coupled to the logic block based on the first voltage level; disabling one or more switching elements that are included in the set of switching elements but not included in the first subset of switching elements; and toggling the first subset of switching elements to power gate the logic block between the first voltage level and zero voltage.