CLOCK PLACEMENT FOR PROGRAMMABLE LOGIC DEVICES

摘要

Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a computer-implemented method includes determining clock resources in a design identifying operations to be performed by a PLD, determining available clock resources of the PLD, determining a flow network model corresponding to the design and the PLD, and determining a clock resource placement based on the flow network model. The flow network model may include a plurality of levels of vertices disposed between source and sink vertices, where vertices are coupled to each other using edges with unit capacity.

主权项

1. A computer-implemented method comprising:
determining clock resources in a design for a programmable logic device (PLD); determining available clock resources of the PLD; determining a flow network model corresponding to the design and the PLD; and determining a clock resource placement based on the flow network model.