Interleaving analog-to-digital converter (ADC) with background calibration

摘要

A system and method are provided of performing background corrections for an interleaving analog-to-digital converter (ADC). An analog input signal s1(t) is accepted having a first frequency f1 and a bandwidth (BW). The method generates a clock at frequency fs, and creates 2 sample clocks with evenly spaced phases, each having a sample clock frequency of fs/2. The method also generates a first tone signal s2(t) having a predetermined second frequency f2 outside BW. The analog input signal and the first tone signal are combined, creating a combination signal, which is sampled using the sample clocks, creating 2 digital sample signals per clock period 1/fs. The 2 digital sample signals are interleaved, creating an interleaved signal. Corrections are applied that minimize errors in the interleaved signal, to obtain a corrected digital output. Errors are determined at an alias frequency f3, associated with the second frequency f2, to obtain correction information.

主权项

1. A method of performing background corrections for an interleaving analog-to-digital converter (ADC), the method comprising:
accepting an analog input signal s1(t) having a first frequency f1 and a bandwidth (BW); generating a clock having a clock frequency fs; creating 2 sample clocks with evenly spaced phases, each having a sample clock frequency of fs/2; generating a first tone signal s2(t) having a predetermined second frequency f2 outside BW; combining the analog input signal and the first tone signal, creating a combination signal; sampling the combination signal using the sample clocks, creating 2 digital sample signals per clock period 1/fs; interleaving the 2 digital sample signals, creating an interleaved signal; applying corrections that minimize errors in the interleaved signal to obtain a corrected digital output; and, determining errors at an alias frequency f3, associated with the second frequency f2, to obtain correction information.