| 摘要 |
A data processor comprising: a register memory comprising an array of memory cells extending in two dimensions and a processing unit. Each cell is addressable by means of an instruction that identifies the row and column of the cell in the array. The processing unit executes instructions identifying a group of cells by means of a first instruction part specifying a pair of coordinates that identify a first cell in the array, and a second instruction part that identifies the configuration of the plurality of cells relative to the first cell. The data processor is arranged to interpret one form of second instruction part as specifying at least one bit of each cell other than the cell specified in the first instruction part that: i) is in the same row as the cell specified in the first instruction part or is in a row adjacent to that row; and ii) is in the same column as the cell specified in the first instruction part or is in a column adjacent to that column. This is useful in video data processing and compression. |
