Method of hierarchical timing closure of VLSI circuits using partially disruptive feedback assertions

摘要

Timing analysis of a chip component using feedback assertions without disrupting the timing of internal latch to latch paths in the chip component maintaining timing accuracy for all the boundary paths. This is achieved by using slack based feedback assertions for non-clock chip inputs and outputs which are used to dynamically derive the arrival time or the required arrival time assertions. The assertions on the clock inputs are not updated via feedback assertions to facilitate non-disruption of the latch to latch path timing. The timing non-disruption of the resulting latch to latch paths of the chip component increases the designer productivity during timing closure resulting in a shortened time to take the chip design through timing closure to manufacturing. This method is applicable for statistical as well as deterministic timing analysis.

主权项

1. A method for timing analysis of a component of an integrated circuit (IC) chip design using slack based feedback assertions, the method comprising:
obtaining, using an electronic design automation system, a slack based feedback assertion for at least one boundary pin of the component, the slack based feedback assertion is generated from the component's parent level of hierarchy; performing timing analysis of the component at the out-of-context level of hierarchy to obtain an arrival time, a required arrival time, and a slack timing value at the at least one boundary pin, the slack timing value is equal to the required arrival time minus the arrival time; computing a new assertion including a new arrival time and a new required arrival time at the at least one boundary pin using the slack based feedback assertion and the result of the timing analysis, wherein the slack timing value obtained during the timing analysis is replaced with a slack timing value of the slack based feedback assertions; and employing the new assertion to perform an updated timing analysis of the component as part of timing closure of the chip design prior to chip manufacturing.