SCALABLE AND RELIABLE NON-VOLATILE MEMORY CELL

摘要

Devices and methods for forming a device are disclosed. The method includes providing a substrate and forming a memory cell pair on the substrate. Each of a memory cell of the memory cell pair includes at least one transistor having first and second gates formed between first and second terminals and a third gate disposed over the second terminal. The first gate serves as an access gate (AG), the second gate serves as a storage gate and the third gate serves as an erase gate (EG). The first cell terminal serves as a bitline terminal and the second cell terminal serves as a source line terminal. The source line terminal is a raised source line terminal and is elevated with respect to the bit line terminal and the source line terminal is common to the memory cell pair.

主权项

1. A device comprising:
a substrate prepared with a memory cell region; and first and second memory cells of a memory cell pair in the memory cell region, wherein the memory cell pair comprises
first and second storage gates (SGs) of the first and second memory cells, wherein a SG includes a primary gate dielectric layer, a floating gate (FG) electrode layer, a control gate (CG) dielectric layer and a CG electrode layer,an elevated source line terminal between the SGs of the memory cell pair, wherein the elevated source line terminal comprises a top surface extending above a top surface of the substrate and below a top surface of the FG electrode layer,an erase gate (EG) over the elevated source line, the erase gate is isolated from first sidewalls of the SGs and source line terminal,first and second access gates (AGs) adjacent to the SGs, andfirst and second bitline terminals adjacent to the first and second AGs.