| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a delay circuit for reducing power consumption and reducing the error of delay time to be generated. <P>SOLUTION: The delay circuit is provided with a plurality of first delay units Y1-Y16 for generating the delay time which is roughly twice as long as unit delay time and a second delay unit X1 for generating the unit delay time. The first delay units are serially connected and the second delay unit X1 is connected to the first delay unit Y16 of the final stage. An external input signal Din is input to the first delay unit Y1 of the initial stage, and the external input signal Din is input to the respective first delay units and the second delay unit. The first delay units and the second delay unit are provided with a switch circuit for delaying and outputting either the output signal of the preceding delay unit of the or the external input signal. A selector 2 for selecting either the output signal of the final first delay unit Y16 or the output signal of the second delay unit X1 is provided. <P>COPYRIGHT: (C)2008,JPO&INPIT</p> |
