FILLING CAVITIES IN AN INTEGRATED CIRCUIT AND RESULTING DEVICES

摘要

A methodology enabling filling of high aspect ratio cavities, with no voids or gaps, in an IC device and the resulting device are disclosed. Embodiments include providing active area and/or gate contacts in a first ILD; forming selective protective caps on upper surfaces of the contacts; forming a second ILD on upper surfaces of the protective caps and on an upper surface of the first ILD; forming a hard-mask stack on the second ILD; forming, in the second ILD and hard-mask stack, cavities exposing one or more protective caps; removing selective layers in the stack to decrease depths of the cavities; and filling the cavities with a metal layer, wherein the metal layer in one or more cavities connects to an upper surface of the one or more exposed protective caps.

主权项

1. A method comprising:
providing active area and/or gate contacts in a first interlayer dielectric (ILD); forming selective protective caps on upper surfaces of the contacts; forming a second ILD on upper surfaces of the protective caps and on an upper surface of the first ILD; forming a hard-mask stack on the second ILD; forming, in the second ILD and hard-mask stack, cavities exposing one or more protective caps; removing selective layers in the stack to decrease depths of the cavities; and filling the cavities with a metal layer, wherein the metal layer in one or more cavities connects to an upper surface of the one or more exposed protective caps, wherein the forming of the hard-mask stack comprises: forming a first dielectric hard-mask (DHM1) layer, a metal hard-mask (MHM) layer, a second dielectric hard-mask (DHM2) layer, a spin-on hard-mask (SOH) layer, and an antireflective coating (ARC) hard-mask layer.