BIPOLAR AND CMOS INTEGRATION WITH REDUCED CONTACT HEIGHT
摘要
Disclosed is a method and structure for an integrated circuit structure that includes a plurality of complementary metal oxide semiconductor (CMOS) transistors and a plurality of vertical bipolar transistors positioned on a single substrate. The vertical bipolar transistors are taller devices than the CMOS transistors. In this structure, a passivating layer is positioned above the substrate, and between the vertical bipolar transistors and the CMOS transistors. A wiring layer is above the passivating layer. The vertical bipolar transistors are in direct contact with the wiring layer and the CMOS transistors are connected to the wiring layer by contacts extending through the passivating layer.
申请公布号
EP1695383(A4)
申请公布日期
2007.12.12
申请号
EP20030819162
申请日期
2003.12.16
申请人
INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人
HE, ZHONG-XIANG;JOSEPH, J., ALVIN;ORNER, A., BRADLEY;RAMACHANDRAN, VIDHYA;ST. ONGE, A., STEPHEN;WANG, PING-CHUAN