TESTING OF CIRCUITS WITH MULTIPLE CLOCK DOMAINS

摘要

A circuit under test (24) has a scan chain comprising flip-flop cells (IOa-c) with inputs and outputs operationally connected to the logic circuits (12). Different clock domains each contain a respective part of the flip-flop cells (lOa-c) that are clocked by a respective domain clock signal(CLKa, CLKb, CLKc). A set of test input patterns is selected, each with an associated combination of domain clock signals that will be selectively enabled to capture a response to the test pattern. The set contains particular test patterns that have the properties that (a) the response captured by a timing sensitive flip-flop cell (1 Oa-c) in a first clock domain is used to detect a fault, (b) the timing sensitive flip-flop cell (lOa-c) receives data dependent on data from a source flip-flop cell (lOa-c) that belongs to a second clock domain different from the first clock domain, and (c) the combination of selectively enabled domain clock signals associated with the particular test pattern comprises the clocks of both the first and second domain. These particular test patterns also have the property that the data value in the source flip-flop cell (1 Oa-c) is identical to a response value captured by the source flip-flop cell (10a-c) for the particular test pattern. Preferably, the set of test patterns is generated for a virtual circuit obtained by additional logic circuits (30, 40, 42) are added to the design of real the circuit under test. The additional logic circuits (30, 40, 42) are designed to selectively enable a dependence of an input signal of the timing sensitive flip-flop cell (1 Oa-c) on data from the source flip-flop cell (1 Oa-c) when the input and output signals of the source flip-flop cell (1Oa-c) are identical and the second domain clock is enabled.