| 发明名称 |
Multi-processor with selectively interconnected memory units |
| 摘要 |
A multi-processor having a plurality of data processing units and memory units has a bus system that selectively interconnects the processing units and the memory units. |
| 申请公布号 |
US2016170925(A1) |
申请公布日期 |
2016.06.16 |
| 申请号 |
US201615052730 |
申请日期 |
2016.02.24 |
| 申请人 |
PACT XPP TECHNOLOGIES AG |
发明人 |
Vorbach Martin |
| 分类号 |
G06F13/40;G06F13/36;G06F9/30;G06F13/16 |
主分类号 |
G06F13/40 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A multi-processor, comprising:
a plurality of data processors, each comprising an arithmetic logic unit; a plurality of memories; and a bus system selectively interconnecting the plurality of data processors and the plurality of memories. |
| 地址 |
MUNICH DE |
