| 发明名称 | Memory circuit including memory devices, a freeze circuit and a test switch | ||
| 摘要 | In one aspect, a memory circuit is provided. The memory circuit includes a first memory device; a second memory device coupled to the first memory device; a freeze circuit coupled to a first output terminal and a second output terminal, where the first output terminal is an output terminal of the first memory device and the second output terminal is an output terminal of the second memory device; and a test switch coupled to the first output terminal and the second output terminal. | ||
| 申请公布号 | US9111641(B1) | 申请公布日期 | 2015.08.18 |
| 申请号 | US201314075781 | 申请日期 | 2013.11.08 |
| 申请人 | Altera Corporation | 发明人 | Patel Rakesh H.;Sinha Shankar Prasad |
| 分类号 | G11C11/00;G11C29/00;G11C13/00 | 主分类号 | G11C11/00 |
| 代理机构 | Mauriel Kapouytian Woods LLP | 代理人 | Mauriel Kapouytian Woods LLP ;Kapouytian Ararat |
| 主权项 | 1. A memory circuit comprising: a first memory device; a second memory device coupled to the first memory device; a freeze circuit coupled to a first output terminal and a second output terminal, wherein the first output terminal is an output terminal of the first memory device and the second output terminal is an output terminal of the second memory device; and a test switch coupled to the first output terminal and the second output terminal. | ||
| 地址 | San Jose CA US | ||