发明名称 Systems and methods for memory controller reference voltage calibration
摘要 An integrated circuit may include a memory controller that interfaces with memory via one or more ports. A given port may be coupled to a comparator that receives data signals from the memory and a reference voltage signal and produces a corresponding output signal that identifies whether the data signals are logic one signals or logic zero signals. The memory controller may include detection circuitry coupled to the port that produces a target reference voltage signal for calibration of the reference voltage signal. The memory controller may include circuitry that produces the reference voltage signal based on control signals received from control circuitry. The control circuitry may generate the control signals to calibrate the reference voltage signal based on the target reference voltage.
申请公布号 US9111603(B1) 申请公布日期 2015.08.18
申请号 US201213409077 申请日期 2012.02.29
申请人 Altera Corporation 发明人 Wang Xiaobao;Sung Chiakang;Huang Joseph
分类号 G11C5/14 主分类号 G11C5/14
代理机构 Treyz law Group 代理人 Tsai Jason;Treyz law Group
主权项 1. An integrated circuit die that communicates with a memory that is external to the integrated circuit die, the integrated circuit die comprising: a port that receives a signal from the memory; detection circuitry coupled to the port, wherein the detection circuitry produces a target reference voltage signal based at least partly on the signal received at the port from the memory; reference circuitry that produces a reference voltage signal based on the target reference voltage signal; and a comparator that receives the signal from the memory through the port and the reference voltage signal and produces a corresponding output signal by comparing the signal from the memory to the reference voltage signal.
地址 San Jose CA US