Incrementer absorption into multiplier logic for programmable logic devices

摘要

Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a computer-implemented method includes receiving a design identifying operations to be performed by a PLD. The computer-implemented method also includes synthesizing the design into a plurality of PLD components. In the computer-implemented method, the synthesizing includes detecting an incrementer-multiplier operation in the design and merging an incrementer portion of the incrementer-multiplier operation with a multiplier portion of the incrementer-multiplier operation to reduce the plurality of PLD components.

主权项

1. A computer-implemented method comprising:
receiving a design identifying operations to be performed by a programmable logic device (PLD); and synthesizing the design into a plurality of PLD components, wherein the synthesizing comprises:
detecting an incrementer-multiplier operation in the design, andmerging an incrementer portion of the incrementer-multiplier operation with a multiplier portion of the incrementer-multiplier operation to reduce the plurality of PLD components, wherein the merged incrementer-multiplier operation comprises at least two addition operations configured to operate substantially in parallel.