发明名称 PLL回路
摘要 A PLL circuit includes a low-pass filter configured to generate a control voltage according to an output current from a charge pump. The low-pass filter includes a preceding stage circuit portion configured to store electric charges according to the output current from the charge pump, and a succeeding stage circuit portion configured to generate the control voltage by receiving the electric charges stored in and transferred from the preceding stage circuit portion. Also, the preceding stage circuit portion includes plural charge storage circuits each including a capacitor, a first switch connected between the capacitor and the charge pump and configured to be driven by a first switch control signal, and a second switch connected between the capacitor and the succeeding stage circuit portion and configured to be driven by a second switch control signal.
申请公布号 JP5811937(B2) 申请公布日期 2015.11.11
申请号 JP20120092863 申请日期 2012.04.16
申请人 发明人
分类号 H03L7/093 主分类号 H03L7/093
代理机构 代理人
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