ISOLATION OF IP UNITS DURING EMULATION OF A SYSTEM ON A CHIP

摘要

A host system receives a description of a design under test (DUT) that includes multiple IP units and is to be emulated by an emulator. The host system compiles the description of the DUT, which includes synthesizing the description, partitioning the DUT, and mapping the partitions to FPGAs included in the emulator that will emulate the DUT. Each IP unit is part of a single partition or partitioned into multiple partitions and mapped to a different set of FPGAs. The host system identifies connections in the DUT between IP units. The host system designates one or more FPGAs of the emulator that have not been allocated to emulate IP units as interface FPGAs. The host system determines a route for each of the identified connections through one of the interface FPGAs. The connections are routed so that there are no direct connections between the sets of FPGAs of two IP units.

主权项

1. A non-transitory computer readable medium storing instructions for isolating emulated units, the instructions to configure a host system to:
identify a first set of field programmable gate arrays (FPGAs) included in an emulator and selected to emulate a first unit in a design under test (DUT); identify a second set of FPGAs included in the emulator and selected to emulate a second unit in the DUT, the second set of FPGAs different than the first set of FPGAs; designate an FPGA included in the emulator for routing connections between units of the DUT, the designated FPGA not part of the first and the second set of FPGAs; and determine a route for a connection between the first unit and the second unit through the designated FPGA.