SMS4 ACCELERATION PROCESSORS HAVING ENCRYPTION AND DECRYPTION MAPPED ON A SAME HARDWARE

摘要

A processing system includes a processing core and a hardware accelerator communicatively coupled to the processing core. The hardware accelerator includes a data register having a plurality of data bits and a key register having a plurality of key bits. The hardware accelerator also includes a data mode selector module to select one of an encrypt mode or a decrypt mode for processing the plurality of data bits. The hardware accelerator further includes a key mode selector module to select one of the encrypt mode or the decrypt mode for processing the plurality of key bits.

主权项

1. A processing system comprising:
a processing core; and a hardware accelerator communicatively coupled to the processing core, the hardware accelerator comprising:
a data register comprising a plurality of data bits;a data mode selector module to select one of an encrypt mode or a decrypt mode for processing the plurality of data bits;a key register comprising a plurality of key bits; anda key mode selector module to select one of the encrypt mode or the decrypt mode for processing the plurality of key bits.