发明名称 SIGNAL PROCESSING CIRCUIT FOR MITIGATING PULLING EFFECT AND ASSOCIATED METHOD
摘要 A signal processing circuit has a first mixer, a first amplifier, and a pulling effect mitigation circuit. The first mixer mixes a first input signal and a first oscillation signal to generate a first output signal, wherein the first oscillation signal is generated by dividing a frequency of a reference clock with a frequency dividing factor. The first amplifier amplifies the first output signal, and generates an amplified output signal at an output terminal of the first amplifier. The pulling effect mitigation circuit is coupled to the output terminal of the first amplifier, and generates a compensation signal to the output terminal for reducing at least an Nth harmonic of the amplified output signal, wherein a value of N is equal to the frequency dividing factor.
申请公布号 US2016164464(A1) 申请公布日期 2016.06.09
申请号 US201514738941 申请日期 2015.06.15
申请人 Mediatek Inc. 发明人 Sun Chih-Hao
分类号 H03D7/14;H03K5/00 主分类号 H03D7/14
代理机构 代理人
主权项 1. A signal processing circuit, comprising: a first mixer, arranged to mix a first input signal and a first oscillation signal to generate a first output signal, wherein the first oscillation signal is generated by dividing a frequency of a reference clock with a frequency dividing factor; a first amplifier, coupled to the first mixer, the first amplifier arranged to amplify the first output signal and generate an amplified output signal at an output terminal of the first amplifier; and a pulling effect mitigation circuit, coupled to the output terminal of the first amplifier, the pulling effect mitigation circuit arranged to generate a compensation signal to the output terminal for reducing at least an Nth harmonic of the amplified output signal; wherein a value of N is equal to the frequency dividing factor.
地址 Hsin-Chu TW