CONTROLLING MEMORY ACCESS CONFLICT OF THREADS ON MULTI-CORE PROCESSOR WITH SET OF HIGHEST PRIORITY PROCESSOR CORES BASED ON A THRESHOLD VALUE OF ISSUED-INSTRUCTION EFFICIENCY

摘要

A multi-core processor system includes multiple cores and memory accessible from the cores, where a given core is configured to detect among the cores, first cores having a highest execution priority level; identify among the detected first cores, a second core that caused access conflict of the memory; and control a third core that is among the cores, excluding the first cores and the identified second core, the third core being controlled to execute for a given interval during an interval when the access conflict occurs, a thread that does not access the memory.

主权项

1. A multi-core processor system comprising
a plurality of cores; and memory accessible from the cores, wherein a given core among the cores is configured to: detect among the cores, first cores having a highest execution priority level, identify based on issued-instruction efficiency calculated based on a cycle count and an issued instruction count of each of the cores, a second core that caused access conflict of the memory with the first cores, and cause a third core other than the first cores and the second core, to execute for a given interval during an interval when the access conflict occurs, a thread that does not access the memory.