Compact and efficient circuit implementation of dynamic ranges in hardware description languages

摘要

Compiling a circuit design includes receiving the circuit design specified in a hardware description language, detecting, using a processor, a slice of a vector within the circuit design, and determining that the slice is defined by a left slice boundary variable and a right slice boundary variable. A hardware description is generated from the circuit design using the processor by including a first shifter circuit receiving the left slice boundary variable as an input signal, a second shifter circuit receiving the right slice boundary variable as an input signal, a control signal generator coupled to the first and second shifter circuits, and an output stage. The output stage, responsive to a control signal dependent upon an output from the first shifter circuit and an output from second shifter circuit, generates an output signal including newly received values from a data signal only for bit locations of the output signal corresponding to the slice.

主权项

1. A method of compiling a circuit design, comprising:
receiving the circuit design specified in a hardware description language; detecting, using a processor, a slice of a vector within the circuit design; determining that the slice is defined by a left slice boundary variable and a right slice boundary variable, wherein the bitwidth of the slice depends upon the left slice boundary variable and the right slice boundary variable; and generating a hardware description comprising a netlist from the circuit design using the processor by including a first shifter circuit receiving the left slice boundary variable as an input signal, a second shifter circuit receiving the right slice boundary variable as an input signal, a control signal generator coupled to the first and second shifter circuits, and an output stage; wherein the output stage, responsive to a control signal dependent upon an output from the first shifter circuit and an output from second shifter circuit, is configured to generate an output signal comprising newly received values from a data signal only for bit locations of the output signal corresponding to the slice.