Method of making high coupling ratio NAND type flash memory

摘要

A new method of fabricating a high coupling ratio Flash EEPROM memory cell is described. A layer of silicon dioxide is grown over the surface of a semiconductor substrate. A layer of silicon nitride is deposited over the silicon dioxide layer and patterned. Silicon nitride spacers are formed on the sidewalls of the patterned silicon nitride layer. The silicon dioxide layer not covered by the patterned silicon nitride layer and the silicon nitride spacers is removed thereby exposing portions of the semiconductor substrate as tunneling windows. A tunnel oxide layer is grown on the exposed portions of the semiconductor substrate. The silicon nitride layer and spacers are removed. A first polysilicon layer is deposited over the surface of the silicon dioxide and tunnel oxide layers and patterned to form a floating gate. An interpoly dielectric layer is deposited over the patterned first polysilicon layer followed by a second polysilicon layer which is patterned to form a control gate. Passivation and metallization complete the fabrication of the NAND type memory cell with improved coupling ratio.