发明名称
摘要 PROBLEM TO BE SOLVED: To keep a stable operation of a post-stage PLL circuit or the like by extracting a stable horizontal synchronizing signal without a nonstandard pulse while keeping the low cost and to keep an excellent image corresponding to a video signal at a weak electric field strength. SOLUTION: A gate processing circuit provided with a monostable multivibrator 2 operated in a non-triggerable mode, a waveform shaping circuit 3 (monostable multivibrator) generates a gate signal SG without jitter to control a switch SW 1 and a signal with a stable horizontal synchronizing pulse width is obtained as a horizontal synchronizing signal H Sync from which a nonstandard pulse is eliminated. Moreover, the switch SW 1 is switched based on a vertical blanking signal V BLK to allow the horizontal synchronizing signal H Sync to be outputted in place of a composite synchronizing signal Sync for a vertical blanking period only via the switch SW 1. Or while a vertical synchronizing signal is not obtained, the composite synchronizing signal Sync is outputted via the switch SW 1.
申请公布号 JP3785632(B2) 申请公布日期 2006.06.14
申请号 JP19980062725 申请日期 1998.03.13
申请人 发明人
分类号 H04N5/08;H03L7/14;H04N5/91;H04N7/08;H04N7/081 主分类号 H04N5/08
代理机构 代理人
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