发明名称 |
LOOP HANDLING IN A WORD-LEVEL NETLIST |
摘要 |
This application discloses an electronic design automation tool configured to identify combinational loops in a word-level netlist, and then modify the word-level netlist based on the presence of the combinational loops. The electronic design automation tool can analyze the word-level netlist to identify a portion of the word-level netlist having at least one characteristic associated with a combinational loop, translate the identified portion of the word-level netlist into a bit-level circuit representation, and utilize the bit-level circuit representation to determine whether the identified portion of the word-level netlist implements the combinational loop. The electronic design automation tool can modify the word-level netlist by replacing the identified combination loop in the word-level netlist with a description of a different circuit, such as a loop buffer, or annotate the presence of the identified combinational loop in the word-level netlist. |
申请公布号 |
US2016224710(A1) |
申请公布日期 |
2016.08.04 |
申请号 |
US201514608603 |
申请日期 |
2015.01.29 |
申请人 |
MENTOR GRAPHICS CORPORATION |
发明人 |
Dua Sunil;Farkash Noam |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
1. A method comprising:
detecting, by a computing system, a presence of a combinational loop in a word-level netlist representation of a circuit design by identifying a portion of the word-level netlist having at least one characteristic associated with the combinational loop, translating the identified portion of the word-level netlist into a bit-level circuit representation, and utilizing the bit-level circuit representation to determine the identified portion of the word-level netlist includes the combinational loop; and modifying, by the computing system, the word-level netlist corresponding to the detected presence of the combinational loop. |
地址 |
Wilsonville OR US |