发明名称 記憶制御装置、不揮発性メモリ、および、メモリ制御方法
摘要 Provided is a memory control device, including a write control unit that sequentially designates a memory block, a write processing unit that writes write data in the designated memory block, a verifying unit that reads read data from the memory block and verifies whether or not the read data matches the write data for each of a plurality of memory cells, a retry inhibiting unit that inhibits a retry process from being performed in a memory cell in which the read data matches the write data among the plurality of memory cells, and a retry control unit that designates at least some memory blocks among the plurality of memory blocks and simultaneously executes the retry process when the read data does not match the write data in any one of the plurality of memory cells in which all the write data is written.
申请公布号 JP5892000(B2) 申请公布日期 2016.03.23
申请号 JP20120184742 申请日期 2012.08.24
申请人 ソニー株式会社 发明人 足立 直大;筒井 敬一;石井 健;大久保 英明;中西 健一;藤波 靖;新橋 龍男;阪井 塁;池谷 亮志
分类号 G11C13/00 主分类号 G11C13/00
代理机构 代理人
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