主权项 |
1. A cell layout within an integrated circuit, comprising:
a first cell comprising a plurality of first poly lines extending along a first direction, wherein said plurality of first poly lines has a first uniform poly pitch and a first uniform poly line width; a second cell being spaced apart from said first cell, said second cell comprising a plurality of second poly lines extending along said first direction, wherein said plurality of second poly lines has a second uniform poly pitch and a second uniform poly line width, wherein said second uniform poly pitch is smaller than said first uniform poly pitch; and a boundary cell being contiguous with said first cell, said boundary cell comprising n stripes of first dummy poly lines and m stripes of second dummy poly lines extending along said first direction, wherein said n stripes of first dummy poly lines have said first uniform poly pitch and said m stripes of second dummy poly lines have said second uniform pitch, wherein n and m are both integers, and wherein n and m are both greater than or equal to 2. |