| 摘要 |
A shift register has an output stage formed by a first transistor connected between an output terminal and a first clock terminal and a second transistor connected between the output terminal and a ground. Third and fourth transistors are connected in series between the gate of the first transistor (first node) and the ground. A second node between the third and fourth transistors is connected to a power source via a fifth transistor. The fifth transistor has its gate connected to the first node. Accordingly, when the third and fourth transistors are turned off to raise the first node in level, the fifth transistor is turned on, whereby a predetermined voltage is applied to the second node.
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