发明名称 受信回路及び受信回路の制御方法
摘要 A receiver circuit includes: a data interpolation switched capacitor circuit which samples a data signal and outputs a voltage value interpolated from a sampled voltage value in correspondence with an interpolation code indicating an interpolation ratio; a comparator which performs comparison between the voltage value outputted from the data interpolation switched capacitor circuit and a threshold value; a phase detection circuit which detects a boundary based on an output of the comparator and decides whether to advance or delay a phase; and an interpolation code generation circuit which generates an interpolation code corresponding to an output of the phase detection circuit, wherein a phase offset related to sampling is imparted and an offset corresponding to an amount of the phase offset is imparted to the threshold value of the comparator.
申请公布号 JP6032080(B2) 申请公布日期 2016.11.24
申请号 JP20130060634 申请日期 2013.03.22
申请人 富士通株式会社 发明人 チャイヴィパース ウィン
分类号 H04L7/033;H03L7/08;H03L7/091 主分类号 H04L7/033
代理机构 代理人
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