| 摘要 |
A PLL frequency synthesizer is provided with a linearization circuit 6 which receives an oscillation frequency control signal V<SUB>T </SUB>from a loop filter LF. The linearization circuit 6 outputs a charge pump current control signal CP<SUB>CONT</SUB>, depending on a potential level of the oscillation frequency control signal V<SUB>T</SUB>. The larger the value of the charge pump current control signal CP<SUB>CONT</SUB>, the higher the potential level. A charge pump CP receives the charge pump current control signal CP<SUB>CONT</SUB>, and causes a current corresponding to the value to flow in or out. Therefore, with a simple circuit structure, loop gain characteristics of the PLL frequency synthesizer can be regulated to be constant. Therefore, even when a variable capacitance element incorporated in a voltage control oscillator has nonlinear characteristics with respect to the potential of the input oscillation frequency control signal, the loop gain characteristics of the PLL frequency synthesizer having the voltage control oscillator can be regulated to be constant.
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