Delay line system and switching apparatus with embedded attenuators

摘要

A monolithically integrated switch configured to operate at an input signal frequency ranging from 0 Hz to 80 GHz. The switch has an input port and two output ports. A first conduction path is provided from the input port to the first output port. A second conduction path is provided from the input port to the second output port. In addition, a first shunting path is provided between the first output port and a reference and a second shunting path is provided between the second output and the reference. In a first mode, the first conduction path and the second shunting path have a low impedance. The second conduction path and the first shunting path have a high impedance. In a second mode, the first conduction path and the second shunting path have a high impedance. The second conduction path and the first shunting path have a low impedance.

主权项

1. A monolithically integrated switch configured to operate at an input signal frequency ranging from 0 Hz to 80 GHz, the switch comprising:
an input port configured to carry the input signal; a plurality of switches configured to provide a plurality of conduction paths; a first output port and a second output port; a first conduction path of the plurality of conduction paths between the input port and the first output port, the first conduction path comprising a first attenuator block comprising one or more shunting resistors and one or more series connected switches of the plurality of switches; a second conduction path of the plurality of conduction paths between the input port and the second output port; a first shunting path of the plurality of conduction paths between the first output port and a reference potential; a second shunting path of the plurality of conduction paths between the second output port and the reference potential; wherein: a low impedance or high impedance of a conduction path of the plurality of conduction paths is selectively provided by one or more switches of the plurality of switches based on a mode of operation of the switch; during a first mode of operation of the switch, the first conduction path and the second shunting path are low impedance conduction paths, and the second conduction path and the first shunting path are high impedance conduction paths, during a second mode of operation of the switch, the second conduction path and the first shunting path are low impedance conduction paths, and the first conduction path and the second shunting path are high impedance conduction paths, and during the first mode of operation, the first attenuator block is configured to reduce a magnitude of voltage standing wave reflections (VSWR) based on a value of a load impedance coupled to the first output port.