PACKAGING SOLUTIONS FOR DEVICES AND SYSTEMS COMPRISING LATERAL GaN POWER TRANSISTORS

摘要

Packaging solutions for large area, GaN die comprising one or more lateral GaN power transistor devices and systems are disclosed. Packaging assemblies comprise an interposer sub-assembly comprising the lateral GaN die and a leadframe. The GaN die is electrically connected to the leadframe using bump or post interconnections, silver sintering, or other low inductance interconnections. Then, attachment of the GaN die to the substrate and the electrical connections of the leadframe to contacts on the substrate are made in a single process step. The sub-assembly may be mounted in a standard power module, or alternatively on a substrate, such as a printed circuit board. For high current applications, the sub-assembly also comprises a ceramic substrate for heat dissipation. This packaging scheme provides interconnections with lower inductance and higher current capacity, simplifies fabrication, and enables improved thermal matching of components, compared with conventional wirebonded power modules.

主权项

1. A semiconductor device structure comprising an assembly of:
a lateral GaN power transistor fabricated on a semiconductor substrate (GaN die) and packaging components comprising a leadframe and a substrate; the GaN die comprising a front surface providing source, drain and gate contact areas for the lateral GaN power transistor and a back surface for die-attach; the leadframe comprising copper, or other metal or metal alloy, having high electrical conductivity and thermal conductivity, the leadframe being patterned to provide source, drain and gate portions corresponding to source, drain and gate contact areas on the front surface of the GaN die; the source, drain and gate contact areas of the GaN die being attached and electrically connected to respective source, drain and gate portions of one side of the leadframe by low inductance connections to form an interposer sub-assembly; source, drain and gate leads of the leadframe extending laterally and vertically from the GaN die to provide source, drain and gate contact surfaces, coplanar with the die-attach surface of the GaN die, for electrical interconnections to respective coplanar contact areas of the substrate; and the die-attach between the back-side surface of the GaN die and the respective source, drain and gate interconnections comprising a layer of interconnect material which is electrically and thermally conductive.