发明名称 PIPELINED SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTER
摘要 A multistage analog-to-digital data conversion, including: a first stage unit configured to process an analog input signal into a first number of most significant bits using a first reference signal, and to output a first stage residue signal; a second stage unit configured to receive and process the first stage residue signal into a second number of remaining least significant bits using a second reference signal; a sampling unit configured to sample the first stage residue signal received from the first stage unit onto the second stage unit with a passive element; and an output unit configured to output a digital value that is a combination of the first number of most significant bits and the second number of remaining least significant bits.
申请公布号 EP3047574(A1) 申请公布日期 2016.07.27
申请号 EP20140772044 申请日期 2014.09.12
申请人 QUALCOMM INCORPORATED 发明人 PARK, HYUNSIK;LIMOTYRAKIS, SOTIRIOS
分类号 H03M1/14;H03M1/46 主分类号 H03M1/14
代理机构 代理人
主权项
地址