发明名称 GROUNDING DUMMY GATE IN SCALED LAYOUT DESIGN
摘要 A semiconductor device includes a gate and a first active contact adjacent to the gate. Such a device further includes a first stacked contact electrically coupled to the first active contact, including a first isolation layer on sidewalls electrically isolating the first stacked contact from the gate. The device also includes a first via electrically coupled to the gate and landing on the first stacked contact. The first via electrically couples the first stacked contact and the first active contact to the gate to ground the gate.
申请公布号 EP3105782(A1) 申请公布日期 2016.12.21
申请号 EP20150702602 申请日期 2015.01.08
申请人 Qualcomm Incorporated 发明人 SONG, Stanley Seungchul;WANG, Zhongze;KWON, Ohsang;RIM, Kern;ZHU, John Jianhong;CHEN, Xiangdong;VANG, Foua;STEPHANY, Raymond George;YEAP, Choh Fei
分类号 H01L21/768;H01L23/485;H01L23/522 主分类号 H01L21/768
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