Semiconductor memory device and method of manufacturing the same

摘要

A connection unit is provided adjacently to the cell array unit and electrically connected to a peripheral circuit unit positioned downwardly of the cell array unit. The cell array unit has a configuration in which a variable resistance layer is provided at intersections of a plurality of word lines extending in a horizontal direction and a plurality of bit lines extending in a vertical direction. The connection unit includes a lower wiring line layer in which a base portion bundling a plurality of the word lines is formed, and a middle wiring line layer and upper wiring line layer formed upwardly thereof. The lower wiring line layer includes: a first penetrating electrode connecting the plurality of word lines and the peripheral circuit unit; and a second penetrating electrode connecting at least one of the middle wiring line layer and upper wiring line layer and the peripheral circuit unit.

主权项

1. A semiconductor memory device, comprising:
a cell array unit; and a connection unit that is provided adjacently to the cell array unit and is electrically connected to a peripheral circuit unit disposed below the cell array unit, the cell array unit including: a plurality of word lines that extend in a first direction and are respectively disposed with a certain spacing in a second direction and a third direction, the second direction intersecting the first direction, and the third direction being a stacking direction that intersects the first direction and the second direction; a plurality of bit lines that extend in the third direction and are respectively disposed with a certain spacing in the first direction and the second direction; a variable resistance layer that is provided on a side surface facing the word line in the bit line and that functions as a storage element at an intersection of the bit line and the word line; a plurality of select gate lines that are provided in a layer upward of the plurality of word lines and that function as a control gate for selecting the bit line; and a plurality of global bit lines that are provided in a layer upward of the plurality of select gate lines and that are electrically connected to the plurality of bit lines via the control gate, and the connection unit including: a lower wiring line layer electrically connected to the plurality of word lines; a middle wiring line layer that is provided on the lower wiring line layer and in which the plurality of select gate lines extending from the cell array unit are formed; and an upper wiring line layer that is provided on the middle wiring line layer and in which the same wiring line layer as the plurality of global bit lines is formed, the lower wiring line layer including: a first penetrating electrode that connects the plurality of word lines and the peripheral circuit unit; and a second penetrating electrode that connects at least one of the middle wiring line layer and upper wiring line layer and the peripheral circuit unit.