发明名称 |
DOUBLE BUS ARCHITECTURE |
摘要 |
The invention relates to an electronic circuit for the processing of images, comprising calculation means, input/output and communication interfaces, and at least one pre-programmed module specifically for the processing of images as well as at least one RAM, characterized in comprising at least one RAM management interface connected to a first bus, called the system bus for the exchange of data between said RAM and the calculation means or input/output interfaces and to a second bus called the image bus, for the exchange of data between said RAM and the pre-programmed module specifically for image processing. The distribution of access rate to the RAM between the two buses being adaptable according to use, a minimum access rate to the RAM being guaranteed for each of the two buses. |
申请公布号 |
WO2004083985(A3) |
申请公布日期 |
2006.12.21 |
申请号 |
WO2004FR00624 |
申请日期 |
2004.03.12 |
申请人 |
TAK'ASIC;VERNIERE, JEAN-PAUL;GAUTIER, PHILIPPE;PAUCARD, BRUNO;LE MAITRE, DIDIER |
发明人 |
VERNIERE, JEAN-PAUL;GAUTIER, PHILIPPE;PAUCARD, BRUNO;LE MAITRE, DIDIER |
分类号 |
G06F3/14;G06T1/60;G09G5/36 |
主分类号 |
G06F3/14 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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