| 主权项 |
1. A processor comprising:
a processor core; and a memory encryption engine (MEE) system coupled to the processor core, the MEE system to provide inline memory encryption and decryption, wherein the MEE system comprises:
an arbiter, wherein the arbiter is to:
receive a first contending request from a first queue and a second contending request from a second queue,
wherein the first contending request is a first request to communicate a first message to an MEE core via a MEE interface of the MEE system, andwherein the second contending request is a second request to communicate a second message to the MEE core via the MEE interface;select the first queue to communicate the first message to the MEE interface or the second queue to communicate the second message to the MEE interface in view of arbitration criteria; andcommunicate the first message or the second message to the MEE interface;the MEE interface, wherein the MEE interface is to:
receive the first message or the second message from the arbiter; andadjust a timing of the first message or the second message to match a timing of the MEE core;the MEE core coupled to the MEE interface, wherein the MEE core is to receive the first message or the second message from the MEE interface; anda memory controller coupled between the MEE core and a main memory, wherein the main memory comprises an enclave to store secure data. |
