DELAY LOCK LOOP BASED FREQUENCY MULTIPLE SYSTEM AND METHOD OF THE SAME

摘要

PURPOSE: A delay lock loop based frequency multiple system and a multiplying method thereof are provided to delete an unnecessary pulse at a constant cycle of an input clock using a harmonic lock prevention block. CONSTITUTION: A harmonic lock prevention block(100) compares a pulse signal of an input clock with a constant cycle of a reference clock. A delay lock loop(200) controls the phase difference between the input clock and the reference clock using a force control signal. The delay lock loop generates a multiple control clock by changing an up signal or down signal to a control voltage. A frequency multiplier(300) generates a multiple clock by multiplying the multiple control clock. A dual loop(400) positions the pulse signal existing in the constant cycle of the multiple clock at the constant cycle of the reference clock. A dithering unit(500) removes the internal noise from the multiple clock by switching the multiple clock before the change and the multiple clock after the change.