发明名称 ROBUST, LOW POWER, RECONFIGURABLE THRESHOLD LOGIC ARRAY
摘要 A field programmable threshold-logic array (FPTLA) includes a number of threshold logic gates and a number of programmable interconnect elements. Each one of the programmable interconnect elements are connected between two or more of the threshold logic gates, such that the programmable interconnect elements route signals between the threshold logic gates. By using threshold logic gates for the FPTLA, the size of the FPTLA may be significantly smaller than conventional solutions. Further, using threshold logic gates results in significant improvements in the computation speed of the FPTLA when compared to conventional solutions.
申请公布号 US2016164526(A1) 申请公布日期 2016.06.09
申请号 US201414903428 申请日期 2014.07.08
申请人 ARIZONA BOARD OF REGENTS ON BEHALF OF ARIZONA STATE UNIVERSITY 发明人 Vrudhula Sarma;Kulkarni Niranjan
分类号 H03K19/177;H03K19/23;H03K19/00 主分类号 H03K19/177
代理机构 代理人
主权项 1. A field programmable threshold-logic array (FPTLA) comprising: a plurality of threshold logic gates; a plurality of programmable interconnect elements each coupled between at least two of the plurality of threshold logic gates and configured to route signals between the plurality of threshold logic gates.
地址 Scottsdale AZ US
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