| 发明名称 |
METHOD AND APPARATUS FOR INJECTING FAULT AND ANALYZING FAULT TOLERANCE |
| 摘要 |
Disclosed herein is a method and apparatus for injecting a fault and analyzing fault tolerance. The fault tolerance analysis apparatus extracts design information from a design. The fault tolerance analysis apparatus may inject a fault into a simulation of the design based on the extracted design information and parameters, and analyzes an influence of the fault on the simulation. Accordingly, in accordance with the fault tolerance analysis apparatus, fault tolerance for the fault injected into the simulation is analyzed, and the effect of the fault tolerance mechanism provided in the design is analyzed. |
| 申请公布号 |
US2016334467(A1) |
申请公布日期 |
2016.11.17 |
| 申请号 |
US201615154829 |
申请日期 |
2016.05.13 |
| 申请人 |
ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE |
发明人 |
CHO Yong-Cheol;KWON Young-Su |
| 分类号 |
G01R31/317;G01R31/3177 |
主分类号 |
G01R31/317 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. An apparatus for analyzing fault tolerance, comprising:
an information extraction unit for extracting design information from a design; a fault injection unit for injecting at least one fault into a simulation of the design based on the extracted design information and a parameter; and a fault tolerance analysis unit for analyzing an influence of the fault on the simulation. |
| 地址 |
Daejeon KR |
