| 摘要 |
PROBLEM TO BE SOLVED: To achieve a semiconductor device having a memory cell structure which achieves reduction in a soft error without complicating a circuit configuration.SOLUTION: In a semiconductor device, an inverter I1 (output part is storage terminal Na) composed of an NMOS transistor N1 and a PMOS transistor P1 and an inverter I2 (output part is storage terminal Nb) composed of an NOS transistor N2 and a PMOS transistor P2 are cross connected, and NMOS transistors N3 and N4 are connected to the storage terminals Na and Nb, respectively. The NMOS transistors N1 and N3 with one electrode being connected to the storage terminal Na are separately formed in P well regions PW0 and PW1, and the NMOS transistors N2 and N4 with one electrode being connected to the storage terminal Nb are separately formed in P well regions PW1 and PW0. The P well regions PW0 and PW1 are formed on the sides opposite to each other across the N well region NW.SELECTED DRAWING: Figure 4 |
