| 摘要 |
The semiconductor device includes a bit line, a transistor, a retention node, and a capacitor. The transistor has a function of charging or discharging the retention node. The capacitor has a function of retaining a potential of the retention node. A voltage greater than the sum of a writing voltage and a threshold voltage is applied to a gate of the transistor. When the transistor is turned on, a first potential is supplied to the bit line with a reference potential in a floating state. A voltage less than the sum of the writing voltage and the threshold voltage is applied to the gate of the transistor. When the transistor is turned on, a second potential is supplied to the bit line with a reference potential in a floating state. With use of the first and second potentials, the threshold voltage of the transistor is calculated without being influenced by parasitic capacitance and variations in the storage capacitance of the capacitor. |
| 主权项 |
1. A test method of a semiconductor device comprising a circuit,
wherein the circuit comprises a first transistor, a capacitor, a retention node, and a first wiring, wherein one of a source and a drain of the first transistor is electrically connected to the first wiring, wherein the other of the source and the drain of the first transistor is electrically connected to the retention node, and wherein a first electrode of the capacitor is electrically connected to the retention node, the test method comprising:
a first step of writing a first potential to the circuit by a first writing operation;a second step of performing a first reading operation on the circuit having undergone the first step, thereby obtaining a potential VWBL1 of the first wiring;a third step of writing a second potential to the circuit by a second writing operation;a fourth step of performing a second reading operation on the circuit having undergone the third step, thereby obtaining a potential VWBL2 of the first wiring; anda fifth step of calculating a threshold voltage Vth of the first transistor, wherein the first writing operation comprises:
a sixth step of supplying a potential VWB to the first wiring;a seventh step of supplying a potential VGM1 to a gate of the first transistor after the sixth step, thereby establishing electrical continuity between the first wiring and the retention node; andan eighth step of turning off the first transistor after the seventh step, thereby bringing the retention node into an electrically floating state, wherein the second writing operation comprises:
a ninth step of supplying the potential VWB to the first wiring;a tenth step of supplying a potential VGM2 to the gate of the first transistor after the ninth step, thereby establishing electrical continuity between the first wiring and the retention node; andan eleventh step of turning off the first transistor after the tenth step, thereby bringing the retention node into an electrically floating state, wherein each of the first reading operation and the second reading operation comprises:
a twelfth step of precharging the first wiring to a third potential;a thirteenth step of bringing the first wiring into an electrically floating state; anda fourteenth step of turning on the first transistor, thereby establishing electrical continuity between the first wiring and the retention node, wherein the potentials VGM1 and VGM2 satisfy the formula (a1), VGM1>VWB+Vth>VGM2, and wherein the fifth step comprises a step of calculating the threshold voltage Vth from the formula (a2), VWBL2/VWBL1=(VWB−Vth)/VWB. |
