发明名称 TEST APPARATUS, PHASE ADJUSTING METHOD AND MEMORY CONTROLLER
摘要 A test apparatus is provided with a timing comparator, which obtains an output value of an output signal outputted from a memory to be tested in a strobe signal timing, a logic comparator, which compares the output value obtained by the timing comparator with an expected value previously generated and outputs comparison results, and a phase adjustment control circuit, which adjusts the strobe signal timing based on the comparison results outputted by the logic comparator. The test apparatus is also provided with a first variable delay circuit, which delays the strobe signal and supplies it to the timing comparator. The phase adjustment control circuit sets a delay quantity of the first variable delay circuit based on the comparison results outputted by the logic comparator. ® KIPO & WIPO 2007
申请公布号 KR20070001264(A) 申请公布日期 2007.01.03
申请号 KR20067023285 申请日期 2006.11.06
申请人 ADVANTEST CORPORATION 发明人 SATO SHINYA
分类号 G11C29/00;G11C7/22;G11C11/407;G11C29/56 主分类号 G11C29/00
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