Methods and system for providing low latency and scalable interrupt collection

摘要

A method for processing an interrupt signal (32,34) within a microprocessor (12) based system is described. The method includes storing a received interrupt signal within an interrupt cause register (62,72,82) of an interrupt controller (60.70,80), outputting an interrupt command from the interrupt controller to an interrupt collector (40), asserting an interrupt signal to the microprocessor from the interrupt collector, and shifting the cause value field into a cause array (50). The interrupt command include an identifier field, a cause register ID field, and a cause value field, and content of the cause value field is based on a content of the interrupt cause register. The interrupt signal is asserted based on receipt of the identifier field and cause register ID field by the interrupt collector, and the shifting of the cause value field into a cause array within the interrupt collector occurs while the microprocessor services the receipt of the identifier field and cause register ID field from the interrupt collector.