| 摘要 |
Each FIR (Finite Impulse Response) filter (106) includes a first input terminal (IA), second input terminal (IB), first output terminal (OA), and second output terminal (OB). Also, m delay elements (d1 through dm) are connected in series between the first input terminal (IA) and first output terminal (OA). Multiple multipliers (K1 through Km) each multiply data at the corresponding one of multiple taps by a predetermined coefficient. An adder circuit (107) outputs, via the second output terminal (OB), product-sum data obtained by adding the data input to the second input terminal (IB) and the output data of the multiple multipliers (K1 through Km). Each FIR filter (106) input is switchable between the data at the input port (IN) and the data output from a different FIR filter (106). |
